----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    08:54:16 06/06/2012 
-- Design Name: 
-- Module Name:    D_FLIP_FLOP - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity D_FLIP_FLOP is
	port(
	CLK		: IN STD_LOGIC;
	RST		: IN STD_LOGIC;
	D			: IN STD_LOGIC;
	
	Q			: OUT STD_LOGIC
	
	);
end D_FLIP_FLOP;

architecture Behavioral of D_FLIP_FLOP is
begin

DFF : process(RST, CLK)
begin
  if RST = '1' then
    Q <= '0';
  elsif rising_edge(CLK) then
    Q <= D;
  end if;
end process DFF;

end Behavioral;

